Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Abstract This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates check node and its associated variable nodes in fully pipelined way, thus allowing to process one row of parity matrix per clock cycle. The work specifically focuses rate 5/6 code size ( N , K ) = (144, 120) symbols over GF(64). synthesis results 28-nm technology show 0.789 M NAND-gates complexity complexity, reaches decoding throughput 0.9 Gbps with 30 iterations. Compared 5G binary LDPC same rate, proposed offers gain 0.3 dB at Frame Error Rate $$10^{-3}$$ 10 - 3 .